Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby

ABSTRACT

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

DESCRIPTION OF THE INVENTION

Field of the Invention

The field of the invention comprises semiconductor devices having viainterconnects and processes for manufacturing these devices.

Background of the Invention

Device interconnections in Very Large Scale Integrated (VLSI) orUltra-Large Scale Integrated (ULSI) semiconductor devices or chipstypically have multilevel structures containing patterns of metal wiringlayers encapsulated in an insulator. Wiring structures within a givenlevel of wiring are separated by an intra level dielectric, while theindividual wiring levels are separated from each other by layers of aninter level dielectric. Conductive vias are formed in the inter leveldielectric to provide inter level contacts between the wiring traces.

The scaling of 2D devices faces challenges such as integration ofdifferent chip functionalities required in advanced processor systems.Industry is looking to 3D integration (3DI) of devices to achieve theseends. One element needed in 3DI schemes comprises through substrate(usually Si) via connections to enable connection between device layersas well as input/output (I/O) connection to the external components.Prior art processes describe etching deep (about 20 micron to about 150micron) through Si vias filled with tungsten or copper as a means toenable these connections. These vias are difficult to fabricate in thetraditional complementary metal oxide semiconductor (CMOS) fabricationenvironment and present cost and reliability issues. Alignment ofpatterns required on the bonded and thinned wafer assembly oftenrequires the use of alignment marks produced using the same deep siliconetch and fill process concurrently with the through via formation. Suchmarks are not easy to produce with good fidelity and as such are notvery conducive for reliable litho alignment. In the present invention wepresent an alternative way to achieve through device layer viaconnections by taking advantage of the use of silicon-on-insulator (SOI)substrates.

Industry experienced problems in standard through joining andface-to-face joining 3DI. Some of these problems include expensive deepSi via etch and fill processing which is difficult to extend not only tosmaller dimensions in the device but also devices having high aspectratios.

Additionally, front-to-back alignment for post-thinning lithography islimited by the quality of the marks formed by deep thru Si filled viasin the process. Also, topography of the back side of the device afterthinning (W and/or Si) can be high and may not be easy to planarize.

One attempt to overcome these and other related problems comprises aso-called via plus riveting approach to 3DI which eliminates deep Sivias but requires etching through the back end of the line (BEOL),middle of the line (MOL), and front end of the line (FEOL) dielectriclayers after the device is fully built. This is an alternate approachthat will allow formation of Cu thru vias.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides structures, articles ofmanufacture and processes that address these needs to not only provideadvantages over the related art, but also to substantially obviate oneor more of the foregoing and other limitations and disadvantages of therelated art. Not only do the written description, claims, abstract ofthe disclosure, and the drawings that follow set forth various features,objectives, and advantages of the invention and how they may be realizedand obtained, but these features, objectives, and advantages will alsobecome apparent by practicing the invention.

To achieve these and other advantages, and in accordance with thepurpose of the invention as embodied and broadly described herein,through vias needed to connect the device layer in the bottom wafer tothe one in the top device layer are formed in the top silicon waferwhich comprises a SOI wafer. Thus the structures involved according tothe invention comprise (1) a top wafer, (2) a top device layer, (3) abottom device layer, (4) a bottom wafer all of which are operativelyassociated with one another to form a 3D semiconductor device. Thesevias comprise through vias, disposed in such a way that they extend fromthe middle of the line (MOL) interconnect of the top wafer to a buriedoxide (BOX) layer of the SOI (top) wafer with appropriate insulationprovided to isolate the vias from the SOI layer.

Middle of the line or MOL, as commonly known in the art, and used aboverefers to the interconnection means between the source, drain and gateelectrodes of individual transistors in semiconductor chips and comprisecontact vias (also known as CA) and the local or very short lengthinterconnection wires that connect the various transistors on the chipinto operational circuitry on the chips. Back end of the line or BEOLrefers to the additional levels of vias and interconnections wiring thatenable connections between groups of transistors (sometimes alsoreferred to as macros) and they tend to be longer than any localinterconnects present in the MOL

FIGS. 1 to 12 comprise side elevations in cross section to illustrate aprocess flow for the 3DI—via to BOX method of manufacturing a deviceaccording to the present invention, and FIG. 13 shows the cross sectionof one embodiment of the device itself.

FIG. 1 shows a close up view of a first SOI wafer cross section afterthe device and MOL regions are fabricated.

FIGS. 2 to 6 show the process sequence that is required to add theadditional features that form the BEOL as well as 3DI unique features tothe point where the wafer is ready for a 3D bonding step.

FIG. 7 shows a close up view of a second SOI wafer cross section afterthe device and MOL regions are fabricated.

FIG. 8 shows this second wafer in cross section after the addition ofBEOL as well as 3DI unique features to the point where the wafer isready for a 3D bonding step.

FIGS. 9 to 12 illustrate the process sequence entailed in aligning andbonding the first wafer on to the second wafer using copper to copperbonding as an illustrative bonding method followed by grinding,polishing and final wiring fabrication on the backside of the BOX layerof the first wafer in the bonded structure.

FIG. 13 illustrates the close up of the final cross section of thebonded 3D device also comprising input output (I/O) terminals in theform of C4 solder balls.

DETAILED DESCRIPTION

To achieve these and other advantages, and in accordance with thepurpose of this invention as embodied and broadly described herein, thefollowing detailed embodiments comprise disclosed examples that can beembodied in various forms.

The specific articles of manufacture, processes, compounds,compositions, and structural details set out herein not only comprise abasis for the claims and a basis for teaching one skilled in the art toemploy the present invention in any novel and useful way, but alsoprovide a description of how to make and use this invention.

The present invention comprises a process and resultant article ofmanufacture made by such process in which through vias needed to connectthe device layer in the bottom wafer to the one in the top device layerare formed in the top silicon wafer which comprises asilicon-on-insulator (SOI) wafer. Through vias are disposed in such away that they extend from the middle of the line (MOL) interconnect ofthe top wafer to the buried oxide (BOX) layer of the top SOI wafer withappropriate insulation provided to isolate them from the SOI devicelayer.

The metal fill for the via can be tungsten or a sacrificial materialthat can be later removed and replaced after the bonding and thinningoperations which we describe later. As the depth of such vias will betypically about a few microns or less, one can use standard CMOSfabrication tools to perform the necessary reactive ion etch (RIE), viafill and planarization steps. Thus the need for deep Si etch and filltools and processes are obviated. Also, the necessary marks required forlithographic alignment from the back side after bonding, grinding andpolishing are also formed with good fidelity in the same process used toform the through device layer vias. Vias are preferably filled withtungsten as it is the commonly used MOL via material. The top SOI waferis bonded to the bottom device wafer using prior art methods such asCu—Cu bonding or thin film transfer joining (combining metal to metal aswell as adhesive based bonding) with or without lock and key alignmentfeatures between the joined wafers. The top SOI wafer is then thinnedusing grinding, polishing and wet or RIE etching such that all of thesilicon substrate is removed, stopping selectively on the BOX layer.Since the etch stop layer of BOX is used, excellent back side planarityis achieved unlike the standard 3DI process where non-uniformities inthe deep silicon etch and fill as well as the back side thinning processlead to a significant topography that need to be planarized.

At this juncture the bottom of the through device layer vias and anyalignment marks made in that level are visible through the BOX layer.Lithography and subsequent processing can be performed in a facilemanner to open and connect to the contacts to the through device layervias, and provide any additional wiring interconnects and form the I/Oterminals for the composite chip to communicate with the externaldevices through the packaging architecture.

In a variant of this process, we can fill the through device vialocations during the initial build with a sacrificial material (such aspoly silicon or amorphous silicon) which can be later etched out afterthe back side contacts are opened. The via openings thus exposed canthen be filled with a BEOL interconnect stack (TaN/Ta/Cu for example).This option can be used if lower electrical and thermal resistance thanthat afforded by tungsten vias is desired.

The remainder of the 3DI process flow in terms of fabrication of thedevice and other wiring layers, joining together of wafers etc are keptthe same in the current method while only the difficulties associatedwith deep silicon via etch and fill are eliminated. This method is analternative to a process flow which employs the formation of the throughdevice vias as the last step in the BEOL processing of the SOI wafer.The present invention avoids the need for etching vias through severalBEOL layers which is required in that process flow.

The foregoing distinguishes the present invention from prior methods andarticles of manufacture and provides a new approach to making thesedevices in that the through via first embodiment of this invention islike the standard 3DI vias, but these vias are only etched to the BOXlayer. The process also utilizes through via etching and isolation atthe MOL level unlike prior methods, and does not require drillingthrough all of the BEOL layers of the through via wafer, unlike the vialast approach. Additionally, the process and article of the inventioncomprise formation of front to back lithography alignment marks createdby about 1 um deep etched features and hence are expected to havesignificantly better shape fidelity than marks obtained after deepsilicon etching and filling. The latter are more prone to shapedistortion resulting from the deep etch and the associated undercut anddimension control issues.

With the present invention, we can preserve and use all favorableelements of the lock and key face to face join process known in the art.In another embodiment of the invention, and if preferred, one can fillsome through vias with a sacrificial fill, which is removed afterthinning, the top wafer and fill with a BEOL fill material selected onthe basis of thermal and/or electrical conductivity.

It is possible to use a bulk silicon (non-SOI) wafer for the bottomwafer (or second wafer in our terminology) if preferred to reduce costs.As this wafer is not processed in the manner of the top (or first wafer)by taking advantage of the BOX layer, it is acceptable to choose a bulksilicon wafer as the bottom wafer in the 3DI stack. Bulk silicon typewafers are used in application specific integrated circuit devices(ASIC's) which can then be combined with devices in the top SOI wafer inthe bonded 3DI structure to produce useful functionalities in the 3Ddevice.

The key challenges addressed by the present invention include, interalia, demonstrating the thinning of a top wafer to BOX (buried oxide)after joining the two wafers together with high yield using joiningmethods known in the art such as transfer joining. It is imperative todemonstrate that the complete removal of the silicon substrate form thetop SOI wafer can be done after bonding using the BOX layer as the etchstop. Other challenges include parasitic issues due to the proximity ofthe interconnect wiring placed on top of the composite structure to thedevices in the SOI layer of top wafer. We theorize that a thicker BOXlayer may alleviate all of the foregoing concerns, but we do not limitourselves by any theory.

The sequence shown in FIGS. 1 to 12 shows one exemplary method of theinvention and the article of manufacture produced thereby using face toface Cu—Cu joining, and tungsten fill for vias and alignment marks. Inother embodiments the approach taken with the present invention can bereadily used along with lock and key transfer joining with adhesives;the alignment marks may be filled with materials other than tungstensuch as molybdenum, ruthenium, nickel, cobalt copper and the like,mixtures thereof and alloys thereof.

-   -   the through vias may be filled with copper but this requires the        use of a sacrificial thru plug via, i.e., a process where we        remove any sacrificial plug after backside thinning followed by        filling with copper.

In another embodiment of the invention, the BOX layer can alleviate bothparasitic issues due to the proximity of the backside BEOL to SOI, butalso mitigate the issue of possible relaxation of channel strain when Siof the first wafer is removed after bonding.

With the present invention, etching BOX, selective to the Si body is nowfeasible. Examples of this process comprise an oxide (or nitride) RIEwith better than about 10:1 selectivity to Si. In this process we employpower of about 100 Watts, pressure of about 40 mT, with a process gasflow comprising CHF3 flow rate of about 40 sccm (standard cubiccentimeters per minute), and oxygen flow rate of about 2.5 sccm. Theoxide etch rate is about 250 A/min blank, about 125 A/min in patternedtrenches, wherein the Si rate is not detectable. In another example weemploy a RIE process developed for a low K dielectric which exhibitsbetter than about 10:1 selectivity of etch rate of oxide to Si. In thisRIE process the power is about 100 W, pressure is about 40 mT, with aprocess gas flow comprising CHF3 flow rate of about 40 sccm, oxygen flowrate of about 2.5 sccm, and nitrogen flow rate of about 10 sccm.

Furthermore, with the present invention, selectivity in etching the backside of the top silicon substrate and stopping on BOX is also feasible.Examples of this process comprise Si RIE with better than about 100:1selectivity to oxide. In this process we employ a power of about 200 W,pressure of about 30 mT, with a process gas flow comprising CFH3 flowrate of about 30 sccm, oxygen flow rate of about 2.5 seem, and sulfurhexafluoride flow rate of about 30 sccm. The Si etch rate is about 10um/60 min, and the oxide rate is about <0.1 um/60 min. We can alsoemploy an alternative process in this aspect of the invention comprisinga KOH wet etch, known to etch Si with high selectivity to BOX.

DESCRIPTION OF PROCESS SEQUENCE FOR ONE ILLUSTRATIVE EMBODIMENT

FIG. 1 shows a close up view of the cross section of a typical SOIdevice wafer known in the art. This wafer which we denote as the firstwafer in our 3DI assembly comprises a buried silicon oxide (BOX) layer1100 disposed on bulk silicon body 1000 of the wafer. The BOX layer 1100is typically about 100 nm thick but can be made thicker if desired. Theactive silicon device channels about 1230 are patterned on top of theBOX layer 1100 and are isolated from other device channels by shallowtrench isolation (STI) regions 1210 typically comprising insulators suchas silicon nitride and silicon oxide. Source/drain silicide contacts1220 are provided to the channels 1230 to achieve electrical connectionto the device. Source drain contacts in turn are connected to contactvias (also known as CA contacts) 1250 which enable interconnection ofseveral adjacent device channels to form useful circuitry. Gateelectrodes 1240 insulated on the sides by spacer dielectric 1245 aredisposed atop a gate insulator 1225 which in turn electrically isolatesthe gate electrode 1240 from the silicon channel 1230. Contacts to thegate electrodes are also made using CA vias (not shown in this view).Biasing the gate electrodes 1240 electrically enables signalamplification to be achieved in the SOI device shown. Also shown in FIG.1 are MOL insulation dielectric 1260, MOL top passivation dielectric1300 and a hard mask layer 1320 to be used in subsequent patterning.While MOL dielectric 1260 can be made of silicon oxide, low dielectricconstant carbon doped oxide and the like, layer 1300 is typically madeof silicon nitride or silicon carbonitride. Hard mask layer 1320 can besilicon oxide, an organic layer or a combination thereof so as toprovide etch selectivity for the subsequent through via patterning stepdescribed next.

In the next step, a photoresist layer is applied on hard mask 1320 andthrough via pattern is imaged in the same and transferred by reactiveion etching (RIE) into the hard mask 1320, passivation layer 1300 andthe MOL dielectric 1260, the BOX layer 1100 stopping on the surface ofthe silicon body 1000. Etching of BOX layer selective to the siliconbody using one of the recipes described earlier is required for thisstep. The resulting cross section after the resist and the hard maskhave been stripped off is shown in FIG. 2. It should be noted that thethrough vias 1500 and 1400 formed thus are located in regions where theydo not intersect the devices or the STI features in the first wafer. Useof appropriate RIE process combinations as described earlier allows theetch process to stop selectively on the silicon body 1000 after etchingthrough the BOX layer 1100.

Next an insulating protective liner 1600 is conformally deposited on allthe exposed surfaces as shown in FIG. 3 and the openings 1400 and 1500are overfilled with a deposition of a fill metal 1700 such as tungsten.Other metal such as molybdenum, ruthenium and the like can also be usedas mentioned earlier and optional adhesion layers or initiation layerscould be deposited prior to the deposition of the metal fill 1700.Chemical vapor deposition (CVD) is best used for the deposition of layer1700 although physical vapor deposition such as sputtering can also beused.

Next the overburden of the layers 1600 and 1700 is removed by a processsuch as CMP and a dielectric cap layer 2000 is deposited on top as shownin FIG. 4. Dielectric cap 2000 can be one of silicon nitride, siliconcarbonitride and the like. The structure now comprises filled vias 1800and 1900 as shown in FIG. 4.

In the next sequence of steps the BEOL layers collectively denoted as3000 in FIG. 5 of this first chip are completed. As noted in FIG. 5 viasof the type 1800 are electrically connected to the BEOL wiring whilevias of the type 1900 are not. Vias of the type 1800 will be used laterfor electrical I/O means while it will be shown that vias of the type1900 serve the purpose of alignment marks in a later process step. Metalfeatures in the top most level of BEOL on this first wafer areexemplified by 3100 in FIG. 5.

In the next set of steps, a metallic bonding pad level typified by 3200is fabricated on some of the top BEOL features 3100 and these pads aresurrounded by and isolated from each other by a recessed dielectriclayer 3300 as depicted in FIG. 6. This structure can be convenientlyfabricated by first fabricating a coplanar inlay of the bonding pads inthe surrounding dielectric by damascene processing and then recessingthe dielectric below the bonding pad by a wet or dry RIE processresulting in the structure shown in FIG. 6. Bonding pads are typicallymade of copper although additional layers such as Ni and Au can be addedto protect the copper surface and enable more facile metal to metalbonding. This completes the fabrication of the first wafer 4000 to beused in the fabrication 3DI device structure.

FIG. 7 shows the second wafer to be used in the exemplary 3DI devicestack after it has been processed through the FEOL and MOL layers. Thenumbering of the various layers and their description follows the samenomenclature as the ones shown in FIG. 1 except that the first digit ofthe numbers identifying the various features has been changed to 5instead of 1 to denote the fact that they are disposed on the secondwafer. Thus the second wafer comprises silicon body 5000, BOX layer5100, FEOL region 5200 further comprising silicon channels 5230, sourcedrain contacts 5220, STI dielectric regions 5210, gate dielectric 5225,gate electrodes 5240, spacer dielectric 5245, CA contacts 5250, MOLdielectric 5260, and MOL passivation 5300. As no vias are patterned andetched into this second wafer those steps performed on first wafer areskipped for the second wafer.

Next BEOL layers 6000 terminated with upper level wiring features 6100and bond pads 6200 are built up in the same manner as described for thefirst wafer resulting in the finished second wafer 7000 shown in FIG. 8.

Next the first wafer 4000 is flipped and aligned to the second wafer7000 as shown in FIG. 9 such that the bond pads 3200 on the first waferand bond pads 6200 on the second wafer are precisely aligned to eachother. Infrared microscopes, split optics and vision system methods canbe used to enable precise alignment and commercial tools capable ofenabling such alignment at one micron or better tolerance are availableand can be used for this step. Bond pads 3200 and 6200 can be chosen tobe of a relative size such that one is larger than the other to enablefull capture of the smaller pad.

In the next step, the two wafers are brought into intimate contact witha concomitant application of elevated pressure and temperature in aninert, reducing gas or vacuum ambient to achieve bonding of the bondingpads 3200 and 6200. Pressures ranging from 50 to 1000 psi andtemperatures ranging from 250 to 450 C can be used. Inert gases such asargon, helium or nitrogen or reducing gases such as hydrogen or forminggas (nitrogen/hydrogen mixture) can be used to keep the surfaces of thebond pads 3200 and 6200 pristine. More preferably a pressure in therange of about 100 to about 300 psi and temperature in the range ofabout 300 C to about 400 C could be used to effect the metal to metalbonding. A lamination press or pressure application using an autoclaveor by means of a gas bladder could be employed to apply the requisitepressure for the bonding. The bonded stack at this stage is shown inFIG. 10.

Once the bonding of the two wafers together is accomplished, in the nextstep the silicon body 1000 of the first wafer (now the top wafer in thebonded stack) is removed by a suitable combination of grinding, CMP andwet or dry RIE methods stopping selectively on the BOX layer 1100. RIEprocesses alluded to earlier are particularly beneficial to use toachieve this selectivity. The structure at this point in the process isshown in FIG. 11.

Additional wiring and interconnect layers 8000 comprising via levels8200 wiring levels 8100 and 8500 are fabricated atop the structure asillustrated in FIG. 12. These layers connect to the circuitry in thesecond wafer 7000 through vias 1800 as shown. Additionally they can alsoprovide other functions such as clock wiring for timing of circuits,power and ground nets required for operating the circuitry in the firstand second wafer. In building up the interconnect layers 8000 the veryfirst wiring layer 8100 uses vias 1900 exposed after the removal of thesilicon body 1000 as alignment marks. By designing the shapes of vias1900 appropriately one can make these features conducive to use asalignment marks with various lithographic tools that may be used forpatterning the interconnect layer 8100. Because of the selective removalprocess used in the present invention, features such as alignment vias1900 can be preserved with very high shape fidelity to enable ease ofrecognition and use for alignment purposes in lithographic imagingtools. Layers 8200 and 8500 can be aligned to features in layer 8100.

In the last sequence a final passivation layer 8550 is applied atop thestructure and contact holes are opened and filled with a bondingmetallurgy and solder 8600 is disposed onto selected locations on thetop metal layer 8500 as shown in FIG. 13. Solder pads 8600 serve as theI/O terminals for the stacked 3DI device wafer. The stacked structure isdiced into individual chips and flip chip joined to suitable packagingcarriers (not shown) for use in product applications.

Although a metal to metal bonding structure and process sequence wasused to illustrate the inventive use of the BOX layer in making a 3DIstack other bonding methods such as transfer joining using metal tometal and adhesive bonding as well as use of lock and key features onthe wafers to enable greater precision in alignment can be readily usedin conjunction with the BOX layer method disclosed herein.

Although only one SOI based device layer is described as attached at thetop of the bottom unthinned wafer, it is possible to extend the presentinventive method to sequentially stack and thin additional SOI baseddevice wafers on top with through vias extending to their respective BOXlayers resulting in a multi-tiered device stack.

In another variant of the inventive method a sacrificial fill materialsuch as polycrystalline or amorphous silicon can be filled in after thestep of forming the via openings 1400 and 1500 to act as a temporaryplace holder that is thermally durable during the subsequent steps ofthe process. This sacrificial material is then removed by a suitableetch process after the step of removing the silicon body 1000 postbonding to the second wafer. A suitable conductive material such ascopper, nickel or cobalt can then be filled into the openings 1400 and1500 made accessible after this etch step. This sequence allows thefilling of the vias 1400 and 1500 choosing from a wider range ofconductive metals as the requirement of thermal stability is lessstringent. Higher conductivity fillers like Cu are more advantageouslyincorporated to form the filled vias 1800 and 1900 by using thisprocessing scheme.

Thus in one embodiment we provide a structure, which we also describeherein as an article of manufacture, comprising at least two bondeddevice layers of which at least one first device layer comprises siliconon insulator (SOI) circuits disposed on a buried oxide (BOX) layer, afirst set of middle of the line (MOL) interconnects and a first set ofback end of the line (BEOL) interconnects disposed thereon, the firstdevice layer further being flipped and bonded atop a second device layerlocated on its parent wafer and comprising a second set of circuits, asecond set of middle of line interconnects and a second set of BEOLinterconnects, and the first and second device layers beinginterconnected together by means of metal filled vias located within thefirst set of MOL interconnects and the BOX layer of the first devicelayer and connecting on one end to bonding pads on the surface closestto the second device layer and on the other end to metal featuresprovided on a third set of interconnects located atop the BOX surfacenot directly in contact with the SOI circuits of the first device layer,thus forming an enhanced 3D device stack.

In another embodiment the structure comprises input output terminalsatop a third set of BEOL interconnects of the at least one first devicelayer to enable connection of the enhanced 3D device stack to packagingsubstrates of an electronic system. The electronic system comprisessemiconductor chips, semiconductor arrays or wafer or IC electroniccomponents and other components such as but not limited tomicro-electro-mechanical (MEMS) components. In another embodiment someof the vias are used as alignment marks in the lithographic fabricationof the third set of BEOL interconnects on the first device layer.Additionally, the vias range in height from about 0.25 micron to about 2um and or from about 0.5 to about 1.0 micron enabling ease of patterningand filling with metal.

Another aspect of the invention comprises a method of fabricating anenhanced 3D device stack comprising the steps of:

-   -   fabricating silicon on insulator (SOI) circuits on a first SOl        wafer with a buried oxide (BOX) layer;    -   providing a first set of middle of the line (MOL) interconnects        for the SOI circuits;    -   patterning and etching a set of vias and alignment marks that        extend from the top surface of the first set of MOL        interconnects to the bottom surface of the BOX layer;    -   filling and planarizing the vias and the alignment marks with a        sacrificial fill material or a metal;    -   completing a first set of BEOL interconnects to connect the SOI        circuits;    -   providing a first set of bonding pad level atop the first set of        BEOL interconnects;    -   fabricating a second device wafer with a set of circuits, second        set of MOL interconnects, a second set of BEOL interconnects and        a second set of bonding pads;    -   flipping the first SOI wafer, positioning it atop the second        device wafer such that the first and the second set of bonding        pads are aligned to each other;    -   bonding the first SOI wafer and the second device wafer together        by applying elevated temperature and pressure to bond the first        and second set of bonding pads;    -   removing the silicon substrate from the first SOI wafer by a        grinding, polishing or etching or combinations thereof and        stopping on the BOX layer and exposing the sacrificial material        filled vias or the metal filled vias and alignment marks;    -   where sacrificial material filled vias are used, etching out the        sacrificial material, refilling and planarizing the vias and        alignment marks with a conductive fill material;    -   fabricating a third set of interconnects atop the BOX layer        using the alignment marks or the sacrificial material filled        alignment marks as reference and connecting to the exposed ends        of the vias; and    -   providing input output pads and solder connection means atop the        top surface of the third set of interconnects to enable        connections to a packaging substrate, where the packaging        substrate comprises semiconductor chips, semiconductor arrays or        wafer or IC electronic components and other components such as        but not limited to micro-electro-mechanical (MEMS) components.        The sacrificial fill material is selected to be thermally stable        through the steps of fabricating the first set of BEOL        interconnects and the step of bonding of the first device wafer        to the second device wafer and removable after the step of        removing the silicon substrate of the first SOI wafer. The        sacrificial fill material may comprise polycrystalline silicon        and amorphous silicon or mixtures thereof, and the conducting        fill material may comprise copper, nickel, ruthenium and cobalt        or mixtures thereof or alloys thereof.

Throughout this specification, abstract of the disclosure, and in thedrawings the inventors have set out equivalents, including withoutlimitation, equivalent elements, materials, compounds, compositions,conditions, processes, structures and the like, and even though set outindividually, also include combinations of these equivalents such as thetwo component, three component, or four component combinations, or moreas well as combinations of such equivalent elements, materials,compositions conditions, processes, structures and the like in anyratios or in any manner.

Additionally, the various numerical ranges describing the invention asset forth throughout the specification also includes any combination ofthe lower ends of the ranges with the higher ends of the ranges, and anysingle numerical value, or any single numerical value that will reducethe scope of the lower limits of the range or the scope of the higherlimits of the range, and also includes ranges falling within any ofthese ranges.

The terms “about,” “substantial,” or “substantially” as applied to anyclaim or any parameter herein, such as a numerical value, includingvalues used to describe numerical ranges, means slight variations in theparameter. In another embodiment, the terms “about,” “substantial,” or“substantially,” when employed to define numerical parameter include,e.g., a variation up to five per-cent, ten per-cent, or 15 per-cent, orsomewhat higher or lower than the upper limit of five per-cent, tenper-cent, or 15 per-cent. The term “up to” that defines numericalparameters means a lower limit comprising zero or a miniscule number,e.g., 0.001. The terms “about,” “substantial” and “substantially” alsomean that which is largely or for the most part or entirely specified.The inventors also employ the terms “substantial,” “substantially,” and“about” in the same way as a person with ordinary skill in the art wouldunderstand them or employ them. The phrase “at least” means one or acombination of the elements, materials, compounds, or conditions, andthe like specified herein, where “combination” is defined above. Theterms “written description,” “specification,” “claims,” “drawings,” and“abstract” as used herein refer to the written description,specification, claims, drawings, and abstract of the disclosure asoriginally filed, or the written description, specification, claims,drawings, and abstract of the disclosure as subsequently amended, as thecase may be.

All scientific journal articles and other articles, including internetsites, as well as any patent or patent application that this writtendescription mentions including the references cited in such scientificjournal articles and other articles, including internet sites, and suchpatent or patent application, are incorporated herein by reference intheir entirety and for the purpose cited in this written description andfor all other disclosures contained in such scientific journal articlesand other articles, including Internet sites as well as any patent orpatent application and the aforesaid references cited therein, as anyone may bear on or apply in whole or in part, not only to the foregoingwritten description, but also the following claims, abstract of thedisclosure, and appended drawings.

Although the inventors have described their invention by reference tosome embodiments, other embodiments defined by the doctrine ofequivalents are intended to be included as falling within the broadscope and spirit of the foregoing written description, and the followingclaims, abstract of the disclosure, and appended drawings.

1-16. (canceled)
 17. An article of manufacture comprising at least two bonded device layers of which at least one first device layer comprises silicon on insulator (SOI) circuits disposed on a buried oxide (BOX) layer having a BOX surface and a first set of middle of the line (MOL) interconnects and a first set of back end of the line (BEOL) interconnects disposed thereon, said at least one first device layer further being flipped and bonded atop a second device layer located on its parent wafer and comprising a second set of circuits, a second set of middle of line interconnects and a second set of BEOL interconnects, and said at least one first device layer and said second device layer being interconnected together by means of metal filled vias located within said first set of MOL interconnects and said BOX layer of said at least one first device layer and connecting on one end to bonding pads associated with said second device layer and on the other end to metal features provided on a third set of BEOL interconnects located atop said BOX surface, where said third set of BEOL interconnects located atop said BOX surface is not directly in contact with said SOI circuits of said at least one first device layer, thus forming an enhanced 3D device stack.
 18. An article of manufacture according to claim 17 further comprising input output terminals atop a third set of BEOL interconnects of said at least one first device layer to enable connection of the said enhanced 3D device stack to packaging substrates of an electronic system.
 19. An article of manufacture according to claim 17 wherein said second set of circuits in said second device layer is one of SOI circuits and bulk silicon circuits.
 20. An article of manufacture according to claim 17 wherein said metal filled vias are filled with a metal comprising tungsten, molybdenum, ruthenium, nickel, cobalt and copper and alloys thereof and mixtures thereof.
 21. An article of manufacture according to claim 17 that incorporates lithographic fabrication of said third set of BEOL interconnects wherein some of said metal filled vias are used as alignment marks in said lithographic fabrication of said third set of BEOL interconnects on said first device layer.
 22. An article of manufacture according to claim 17 wherein said metal filled vias range in height from about 0.25 micron to about 2 um enabling ease of patterning and filling with metal.
 23. An article of manufacture according to claim 17 wherein said metal filled vias range in height from about 0.5 to about 1.0 micron enabling ease of patterning and filling with metal.
 24. A product made by the process of fabricating an enhanced 3D device stack comprising the steps of: fabricating silicon on insulator (SOI) circuits on a first SOI wafer with a buried oxide (BOX) layer; providing a first set of middle of the line (MOL) interconnects for said SOI circuits; patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer; filling and planarizing said vias and said alignment marks with metal; completing a first set of BEOL interconnects to connect said SOI circuits; providing a first set of bonding pad level atop said first set of BEOL interconnects; fabricating a second device wafer with a second set of circuits comprising a second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads; flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other; bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads; removing the silicon substrate from said first SOI wafer by a grinding, polishing and etching or combinations thereof and stopping on said BOX layer and exposing said metal filled vias and alignment marks; fabricating a third set of interconnects atop said BOX layer using said alignment marks as reference and connecting to the exposed ends of said vias; and providing input output pads and solder connection means atop the top surface of said third set of interconnects to enable connections to a packaging substrate.
 25. A product according to claim 24 wherein the metal used to fill said vias in said first device wafer comprises tungsten, molybdenum, ruthenium, nickel and cobalt and alloys thereof and mixtures thereof.
 26. A product according to claim 24 including the process steps associated with the fabrication of the first SOI wafer, comprising said bonding, and providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer, and further providing additional interconnects atop said BOX layer.
 27. A product according to claim 26 wherein said process of providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer is repeated using additional SOI wafers so as to enable the incorporation of more than two device layers in the 3D stack.
 28. A product according to claim 24 wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits.
 29. A product according to claim 24 wherein said vias range in height from about 0.25 micron to about 2 um enabling ease of patterning and filling with metal.
 30. A product according to claim 25 including the process steps associated with the fabrication of the first SOI wafer, comprising said bonding, and further providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer, and further providing additional interconnects atop said BOX layer.
 31. A product according to claim 25 wherein said process of providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer is repeated using additional SOI wafers so as to enable the incorporation of more than two device layers in the 3D stack.
 32. A product according to claim 25 wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits.
 33. A product according to claim 25 wherein said vias range in height from about 0.25 micron to about 2 um enabling ease of patterning and filling with metal.
 34. A product according to claim 26 including the process steps associated with the fabrication of the first SOI wafer, comprising said bonding, and further providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer, and further providing additional interconnects atop said BOX layer.
 35. A product according to claim 34 wherein said process of providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer is repeated using additional SOI wafers so as to enable the incorporation of more than two device layers in the 3D stack.
 36. A product according to claim 26 wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits. 